Thin film transistor having a graded metal oxide layer

ABSTRACT

Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor may include a gate; a channel layer; a source and a drain, the source and the drain being formed of metal; and a metal oxide layer, the metal oxide layer being formed between the channel layer and the source and the drain. The metal oxide layer may have a gradually changing metal content between the channel layer and the source and the drain.

PRIORITY STATEMENT

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 10-2007-0020528, filed on Feb. 28, 2007, in the KoreanIntellectual Property Office, the entire contents of which areincorporated herein by reference.

BACKGROUND

1. Field

Example embodiments relate to a switching device and a method ofmanufacturing the same, and more particularly, to a thin film transistorand a method of manufacturing the same.

2. Description of Related Art

Thin film transistors may be used as switching devices for flat paneldisplay devices, for example, a liquid crystal display device or anorganic light emitting display device.

The mobility or leakage current of a thin film transistor may varysignificantly depending on the material and state of a channel layer ofthe thin film transistor.

The majority of the channel layer of the thin film transistor inconventional liquid crystal display devices may be an amorphous siliconlayer. If the channel layer of the thin film transistor is an amorphoussilicon layer, the charge mobility may be about 0.5 cm²/Vs, which islow, and thus, it may be difficult to increase the operation speed ofthe conventional liquid crystal display devices.

Accordingly, research is being conducted to find ways to use a ZnO basedmaterial layer, for example, a Ga—In—Zn—O layer, having greater chargemobility than an amorphous silicon layer, as a channel layer for a thinfilm transistor. The mobility of the Ga—In—Zn—O layer may be severaltens of times greater than that of the amorphous silicon layer, andthus, it may significantly increase the operation speed of a liquidcrystal display device.

SUMMARY

Example embodiments may provide a thin film transistor which may haveimproved characteristics due to improved contact between a source and adrain of the thin film transistor.

Example embodiment may also provide a method of manufacturing the thinfilm transistor.

Example embodiments may provide a thin film transistor (TFT) which mayinclude a gate; a channel layer; a source and a drain, the source andthe drain being formed of metal; and a metal oxide layer, the metaloxide layer being formed between the channel layer and the source andthe drain.

The metal oxide layer may have a gradually changing metal contentbetween the channel layer and the source and the drain.

The metal content in the metal oxide layer may be gradually increased ordecreased in a direction toward the channel layer.

The metal oxide layer may be a stoichiometric layer or anon-stoichiometric layer.

The metal oxide layer may include a transition metal having an oxidationcharacteristic higher than or similar to that of ZnO.

The source and the drain may be double-layers formed of metal.

The channel layer may be an oxide semiconductor layer.

The metal contained in the metal oxide layer may be the same as themetal of the source and the drain.

The gate may be formed above or under the channel layer or buried in thechannel layer.

The transition metal may be one selected from the group consisting ofAl, Ti, Mo, Cr or W.

The source and the drain may be formed of at least one selected from thegroup consisting of Ti, Mo, Cr, W, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Co,Sb, V, Ru, Pt, Pd, Zn, and Mg.

The oxide semiconductor layer may be an a(In₂O₃).b(Ga₂O₃).c(ZnO) or ana(In2O3).b(ZnO).c(SnO) (where a, b, and c are integers satisfying a≧0,b≧0, and c>0, respectively).

Example embodiments may provide a method of manufacturing a thin filmtransistor (TFT) which may include forming a gate on a substrate,forming a gate insulating layer covering the gate on the substrate,forming a channel layer on the gate insulating layer, and forming asource and a drain by sequentially stacking a metal oxide layer and ametal layer on the channel layer and the gate insulating layer.

After forming the metal oxide layer and the metal layer, annealing aresultant structure may be performed.

The annealing may be performed between 250° C.˜450° C. in a nitrogenatmosphere using a furnace, a rapid thermal annealing (RTA), or laser.

According to at least one example embodiment, the channel layer may befirst formed on the substrate, and the source and the drain may beformed by sequentially stacking the metal oxide layer and the metallayer on the channel layer and the substrate, and the gate and the gateinsulating layer may be formed after forming the source and the drain byforming the gate insulating layer to cover the channel layer, the metaloxide layer, and the metal layer, and forming the gate on the gateinsulating layer.

Example embodiments may provide a method of manufacturing a thin filmtransistor (TFT) which may include forming a gate on a substrate,forming a gate insulating layer covering the gate on the substrate,forming a channel layer on the gate insulating layer, stacking a metallayer on the channel layer and the gate insulating layer, and forming ametal oxide layer between the metal layer and the channel layer.

The metal oxide layer may be formed by annealing a resultant structureincluding the metal layer.

The annealing may be performed using a furnace, rapid thermal annealing(RTA), or a laser.

The annealing may be performed between 250° C.˜450° C. in an atmospherecontaining nitrogen or oxygen.

The annealing may be performed in an oxygen atmosphere between 250°C.˜450° C.

According to at least one example embodiment, the channel layer may befirst formed on the substrate, and the metal layer may be formed on thechannel layer and the substrate, and the gate insulating layer may beformed to cover the metal layer and the channel layer, and the metaloxide layer may be formed after forming the gate on the gate insulatinglayer.

Additionally, the channel layer may be first formed on the substrate,and the metal layer may be formed on the channel layer and thesubstrate, and then the metal oxide layer may be formed, and the gateinsulating layer may be formed to cover the metal layer, the metal oxidelayer, and the channel layer, and the gate may be formed on the gateinsulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The patent or application file contains at least one drawing executed incolor. Copies of this patent or patent application publication withcolor drawing will be provided by the Office upon request and payment ofthe necessary fee.

The above and other features and advantages of example embodiments willbecome more apparent by describing in detail example embodiments withreference to the attached drawings. The accompanying drawings areintended to depict example embodiments and should not be interpreted tolimit the intended scope of the claims. The accompanying drawings arenot to be considered as drawn to scale unless explicitly noted.

FIG. 1 is a plan view of a thin film transistor (TFT) according to atleast one example embodiment.

FIG. 2 is a cross-sectional view of a cut along line 2-2′ of FIG. 1.

FIGS. 3 through 8 are graphs showing electrical characteristics offirst, second, and third TFTs, according to the example embodiments.

FIG. 9 is a graph showing the drain current (I_(d))-drain voltage(V_(d)) of the first TFT, according to at least one example embodiment.

FIG. 10 is a graph showing the gate voltage-the source and drain currentcharacteristics of a TFT, according to at least one example embodiment,used in experiments.

FIG. 11 is a graph showing the drain current-drain voltagecharacteristic of the TFT used in experiments.

FIGS. 12 through 15 are cross-sectional views of a method ofmanufacturing a TFT according to at least one example embodiment.

FIG. 16 is a graph showing source-drain current (I_(ds)) versus thethickness of a metal oxide layer based on the method of manufacturing aTFT, according to at least one example embodiment.

FIGS. 17 through 19 are cross-sectional views of a method ofmanufacturing a TFT according to at least one example embodiment.

FIGS. 20 and 21 are graphs showing electrical characteristics of the TFTbased on the annealing temperature in the method of manufacturing a TFT,according to at least one example embodiment.

FIGS. 22 and 23 are photographic images of a silicon oxide layer, achannel layer, and a metal layer that are sequentially stacked when notannealed and when annealed at 350° C., respectively.

FIGS. 24 and 25 are graphs showing the material components along 1-1′ ofFIGS. 22 and 23.

FIG. 26 is a cross-sectional view of a top gate TFT to which the exampleembodiments may be applied.

DESCRIPTION OF EXAMPLE EMBODIMENTS

Detailed example embodiments are disclosed herein. However, specificstructural and functional details disclosed herein are merelyrepresentative for purposes of describing example embodiments. Exampleembodiments may, however, be embodied in many alternate forms and shouldnot be construed as limited to only the embodiments set forth herein.

Accordingly, while example embodiments are capable of variousmodifications and alternative forms, embodiments thereof are shown byway of example in the drawings and will herein be described in detail.It should be understood, however, that there is no intent to limitexample embodiments to the particular forms disclosed, but to thecontrary, example embodiments are to cover all modifications,equivalents, and alternatives falling within the scope of exampleembodiments. Like numbers refer to like elements through the descriptionof the figures.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of example embodiments. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it may be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between element should be interpreted in a like fashion(e.g., “between” versus “directly between”, “adjacent” versus “directlyadjacent”, etc.).

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises”, “comprising”, “includes” and/or “including”, when usedherein, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

It should also be noted that in some alternative implementations, thefunctions/acts noted may occur out of the order noted in the figures.For example, two figures shown in succession may in fact be executedsubstantially concurrently or may sometimes be executed in the reverseorder, depending upon the functionality/acts involved.

The example embodiments will now be described more fully with referenceto the accompanying drawings. The thicknesses of layers or regionsillustrated in the drawings may be exaggerated for clarity.

First, a thin film transistor (TFT) according to at least one exampleembodiment will be described.

FIG. 1 is a plan view of the TFT according to at least one exampleembodiment. In FIG. 1, Reference numeral 42 denotes an insulating layerwhich may cover a substrate. The insulating layer 42 may be a siliconoxide layer having a thickness of 100 nm. Reference numerals 44, 50, and52 respectively denote a gate, a source, and a drain. The positions ofthe source 50 and the drain 52 of the TFT may be exchanged with eachother. A portion of each of the source 50 and the drain 52 may protrudetoward each other and may form protrusions 50P and 52P. The spacebetween a protrusion 50P of the source 50, which may have apredetermined or desired width W, and a protrusion 52P of the drain 52,which may have the same width W, is a channel region which may have apredetermined or desired length L. The source 50 and the drain 52 may bemetal layers. For example, the source 50 and the drain 52 may be metallayers formed of at least one selected from the group consisting of Ti,Mo, Cr, W, Pt, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Co, Sb, V, Ru, Pt, Pd,Zn, and Mg. Hence, the source 50 and the drain 52 may be pure metallayers or metal alloy layers.

Additionally, the source 50 and the drain 52 may be any electricallyconductive metal layers. The source 50 and the drain 52 may also bedouble-layers formed of two sequentially stacked metal layers. Thesource 50 and the drain 52 may be formed of two sequentially stackedmetal layers selected from the group consisting of Ti, Mo, Cr, W, Pt,Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Co, Sb, V, Ru, Pt, Pd, Zn, and Mg, forexample, a titanium layer and a platinum layer sequentially stacked.

FIG. 2 is a cross-sectional view of a cut along 2-2′ of FIG. 1,according to at least one example embodiment. Referring to FIG. 2, theinsulting layer 42 may be formed on a substrate 40, which may be asemiconductor substrate, for example, a silicon substrate. A gate 44 maybe formed on a predetermined or desired region of the insulating layer42. The gate 44 of the TFT may be formed of molybdenum or otherconductive materials. A gate insulating layer 46 may be formed on theinsulating layer 42 and may cover the gate 44, and the gate insulatinglayer 46 may be a silicon oxide layer. A channel layer 48 may be formedon the gate insulating layer 46 and may cover the gate 44, and thechannel layer 48 may be an oxide semiconductor layer, for example, aG-I—Z—O layer, that is, [a(In₂O₃).b(Ga₂O₃).c(ZnO) layer] or[a(In2O3).b(ZnO).c(SnO)] (where a, b, and c are integers satisfying a≧0,b≧0, and c>0, respectively). A first metal oxide layer 54 and a secondmetal oxide layer 56 may be formed separate from each other on thesurface of the channel layer 48, and the first and second metal oxidelayers 54 and 56 may face each other. The first metal oxide layer 54 maybe formed between the source 50 and the channel layer 48. The secondmetal oxide layer 56 may be formed between the drain 52 and the channellayer 48. The first metal oxide layer 54 may be formed on a side of thechannel layer 48 and may be extended over an upper surface of thechannel layer 48. The second metal oxide layer 56 may be formed onanother side of the channel layer 48 and may be extended over the uppersurface of the channel layer 48. The source 50 may be in contact with anupper surface of the first metal oxide layer 54, and the drain 52 may bein contact with an upper surface of the second metal oxide layer 56. Thefirst and second oxide layers 54 and 56 may be a stoichiometric or anon-stoichiometric layer. Additionally, the first and second oxidelayers 54 and 56 may be metal oxide layers having a gradually changingmetal content. For example, the first and second metal oxide layers 54and 56 may be titanium oxide layers in which the content of titanium maybe increased or decreased in a direction from the source 50 and thedrain 52 to the channel layer 48. Additionally, the first and secondmetal oxide layers 54 and 56 may include a transition metal which mayhave a higher oxidation characteristic than ZnO, and the transitionmetal may be Al, Ti, Mo, Cr or W. The first and second metal oxidelayers 54 and 56 may form ohmic contacts with the source 50 and thedrain 52, respectively, and may form a hetero-junction with the channellayer 48; and the thickness of the first and second metal oxide layers54 and 56 may be 3 Å-300 Å.

FIGS. 3 through 8 are graphs showing electrical characteristics of afirst, a second, and a third TFT, according to the example embodiments;

In the first TFT, the source 50 and the drain 52 respectively aresequentially stacked Ti/Pt layer; the first and second metal oxidelayers 54 and 56 are titanium oxide layers; the channel layer 48 is aG-I—Z—O layer, for example, a GIZO221 layer; a ratio of the width W ofthe protrusions 50P and 52P of the source 50 and the drain 52 to thelength L of the channel layer 48 (W/L) is 50/20; and the first TFT isannealed for a predetermined or desired period of time, for example, 1hour, at 350° C. FIG. 3 is a graph showing the current-voltagecharacteristic of the first TFT, according to at least one exampleembodiment. FIG. 4 is a graph showing variations in the current betweenthe source 50 and the drain 52 according to the voltage that is appliedto the drain 52 when no voltage is applied to the gate 44 in the firstTFT, according to at least one example embodiment.

In FIG. 3, first through third graphs G1 through G3 show thecharacteristics between a gate voltage V_(g) and a source-drain currentIds when voltages of 0.1 V, 5 V, and 10 V are applied to the drain 52.

Referring to FIG. 3, when the gate voltage V_(g) is 0 V regardless of avoltage that is applied to the drain 52, the source-drain current I_(ds)of the TFT is substantially 0, and as the gate voltage V_(g) that isapplied is increased to be greater than 0 V, a significant source-draincurrent I_(ds) is measured at a threshold voltage or higher.Additionally, referring to FIG. 4, when no voltage is applied to thegate 44 and a voltage from 0 V to +4 V or −4 V is applied to the drain52, there is no current flowing between the source 50 and the drain 52,which may indicate that the first TFT is operating in an enhanced mode.

FIGS. 5 and 6 show electrical characteristics of the second TFT,according to at least one example embodiment. The second TFT is the sameas the first TFT used to obtain the results of FIGS. 3 and 4 except thatthe second TFT includes the source 50 and the drain 52 which arerespectively formed of a chromium layer and a platinum layer that aresequentially stacked, and the first and second metal oxide layers 54 and56 are formed of chromium oxide layers. In FIG. 5, first through thirdgraphs G1 through G3 show the characteristics between a gate voltageV_(g) and a source-drain current I_(ds) when voltages of 0.1 V, 5 V, and10 V are applied to the drain 52.

Referring to FIG. 5, the second TFT may show similar electricalcharacteristics to the current-voltage characteristics of the first TFTas illustrated in FIG. 3. Additionally, referring to FIG. 6, as novoltage is applied to the gate 44, the current flowing between thesource 50 and the drain 52 of the second TFT does not flow when thevoltage that is applied to the drain 52 is from 0 V to +2 V or −2 V andthus, the second TFT is operating in an enhanced mode.

FIGS. 7 and 8 show electrical characteristics of the third TFT accordingto at least one example embodiment. The third TFT is the same as thefirst TFT except for the configuration of the source 50 and the drain 52and the first and second metal oxide layers 54 and 56. Thus, the thirdTFT includes the source 50 and the drain 52 respectively formed of atungsten layer and a platinum layer that are sequentially formed. Thefirst and second metal oxide layers 54 and 56 are tungsten oxide layers.In FIG. 7, first through third graphs G1 through G3 show thecharacteristics between a gate voltage V_(g) and a source-drain currentI_(ds) when voltages of 0.1 V, 5 V, and 10 V are applied to the drain52.

Referring to FIG. 7, the current-voltage characteristic of the third TFTmay be similar to the electrical characteristics of the first and secondTFTs. Referring to FIG. 8, as no voltage is applied to the gate 44, thecurrent flowing between the source 50 and the drain 52 of the second TFTdoes not flow when the voltage that is applied to the drain 52 is from 0V to +4 V or −2 V, and thus, the third TFT is also operating in anenhanced mode.

Because the TFTs according to example embodiments may operate in anenhanced mode, there may be no leakage current in the TFTs according tothe example embodiments whereas leakage current may occur in theconventional TFT operating in a depletion mode.

FIG. 9 shows drain current (I_(d)) versus drain voltage (V_(d))characteristics of the first TFT, according to at least one exampleembodiment. First and second graphs G11 and G22 show I_(d)-V_(d)characteristics measured at a voltage lower than 10 V (e.g., 0.1 V orless than 5 V) that are applied to the gate 44. Third through fifthgraphs G33 through G55 show I_(d)-V_(d) characteristics when voltages of10 V, 15 V, and 20 V are applied to the gate 44. Referring to the firstthrough fifth graphs G11 through G55, when a voltage that is applied tothe gate 44 is 10 V or greater, the drain current I_(d) may increase asthe drain voltage V_(d) is increased. Additionally, the drain currentI_(d) may increase as the voltage that is applied to the gate 44 isincreased.

Referring to FIG. 9, the TFT according to the example embodiments maydemonstrate improved leakage current as compared to the conventional TFTwhere the drain current I_(d) is observed when a voltage greater than 0V is applied to a gate, regardless of the amount of voltage greater than0V that is applied to the gate.

Experiments were conducted in order to determine how the TFTcharacteristics may vary when the TFT does not include the first andsecond metal oxide layers 54 and 56.

To conduct the experiments, the first and second metal oxide layers 54and 56 were removed from the TFT and the source 50 and the drain 52 wereformed of platinum layers. The rest of the conditions were set the sameas the first TFT.

FIG. 10 shows the gate voltage V_(g)-source/drain current I_(ds)characteristics of the TFT used in the experiments, according to atleast one example embodiment. FIG. 11 shows drain current-drain voltagecharacteristic of the TFT used in the experiments, according to at leastone example embodiment.

Referring to FIG. 10, no source/drain current I_(ds) is measured untilthe gate voltage V_(g) reaches 10 V or higher. When the gate voltage is10 V or greater, the source/drain current I_(ds) is measured, however,the amount of source/drain current I_(ds) is about 10⁻¹¹ (A), which isvery low, and may be regarded as no source/drain current I_(ds). Themeasured source/drain current I_(ds) as shown in FIG. 11 is about 10⁻¹¹(A), which is very low and may be regarded as no flowing drain currentI_(d).

As can be seen from the results of FIGS. 10 and 11, when there are nofirst and second metal oxide layers 54 and 56 between the source 50 andthe drain 52 and the channel layer 48, barriers blocking carriertransportation may be formed between the source 50 and the drain 52, andthe channel layer 48. Thus, the presence of the first and second metaloxide layers 54 and 56 may lower the barriers.

Hereinafter, a method of manufacturing a TFT according to at least oneexample embodiment will be described.

Referring to FIG. 12, the insulating layer 42 may be formed on thesubstrate 40. The substrate 40 may be a silicon substrate. Theinsulating layer 42 may be formed of a silicon oxide layer to athickness of about 100 nm. The gate 44 may be formed on a predeterminedor desired region of the insulating layer 42. The gate 44 may be formedof a conductive material, for example, molybdenum (Mo).

Referring to FIG. 13, the gate insulating layer 46 may be formed on theinsulating layer 42 covering the gate 44. The gate insulating layer 46may be formed of a silicon oxide layer. The channel layer 48 may beformed on a predetermined or desired region of the gate insulating layer46 which may cover the gate 44. The channel layer 48 may be formed tocross over the gate 44. The channel layer 48 may be formed of an oxidesemiconductor layer, for example, a G-I—Z—O layer.

Referring to FIG. 14, a photosensitive pattern P1 may be formed on thesubstrate 40 to expose a portion of the channel layer 48 and a portionof the gate insulating layer 46. The photosensitive pattern P1 may covera portion of an upper surface of the channel layer 48. The portions ofthe photosensitive pattern P1 that cover the gate insulating layer 46around the channel layer 48 may be separate from the channel layer 48.Accordingly, after the photosensitive pattern P1 is formed, the rest ofthe channel layer 48, except for a portion which may cover the gate 44,may be exposed. Additionally, a portion of the gate insulating layer 46between the channel layer 48 and the photosensitive pattern P1 may beexposed. A source and a drain may be formed in the exposed regions afterthe photosensitive pattern P1 is formed. The planar surface of theexposed portions after the photosensitive pattern P1 is formed may bethe same as the surface covered by the source 50 and the drain 52 ofFIG. 1.

Referring to FIG. 15, a metal oxide layer 70 and a metal layer 72 may beformed on the exposed portions of the channel layer 48, and the gateinsulating layer 46. The metal oxide layer 70 and the metal layer 72 mayalso be sequentially stacked on the photosensitive pattern P1. The metaloxide layer 70 may be formed of the same material as the first andsecond metal oxide layers 54 and 56 of the TFT according to at least oneexample embodiment. The metal layer 72 may be formed of the samematerial as the source 50 and the drain 52 of the TFT according to theexample embodiments. The metal oxide layer 70 may be formed to athickness of 3 Å-300 Å, and the metal layer 72 may be formed to athickness of 500 Å-1500 Å. The metal layer 72 may be formed to athickness of about 500 Å when the metal layer 72 is a titanium layer ora platinum layer. The metal layer 72 may be formed as a single layer ora double layer. If the metal layer 72 is a double layer, an upper layermay be a platinum layer. The metal oxide layer 70 and the metal layer 72may be formed using a sputtering method, a deposition method usingelectron beams, an atomic layer deposition method, or a chemical vapordeposition method.

If the metal oxide layer 70 is formed using the sputtering method, apredetermined or desired amount of sputtering gas and oxygen may besupplied to a reaction chamber. The sputtering gas may be argon (Ar)gas. If the metal oxide layer 70 is a titanium oxide (TiO₂) layer, themetal oxide layer 70 may be formed by supplying Ar gas and oxygen to thereaction chamber such that the content of Ar gas is 35% and the oxygencontent is about 15%, and by applying power of 1 kW to a sputteringtarget. The pressure of the reaction chamber may be maintained constantat about 3 mtorr.

Among the metal oxide layers 70, which may be stacked on the exposedregion of the channel layer 48 and the gate insulating layer 46, thelayer to the left of gate 44 may correspond to the first metal oxidelayer 54 in FIG. 2, and the layer to the right of gate 44 may correspondto the second metal oxide layer 56 in FIG. 2. And among the metal layers72, which may be formed on the metal oxide layers 70, the layer to theleft of gate 44 may correspond to the source 50 in FIG. 2 and the layerto the right of gate 44 may correspond to the drain 52 in FIG. 2.

Furthermore, the photosensitive pattern P1 may be lifted off from theresultant structure illustrated in FIG. 15 along with the metal oxidelayer 70 and the metal layer 72, which may be stacked on thephotosensitive pattern P1. After the photosensitive pattern P1 is liftedoff, the TFT as illustrated in FIG. 2 may be formed.

However, a portion of the metal oxide layer 70 corresponding to thefirst and second metal oxide layers 54 and 56 of FIG. 2 (hereinafter“first portion”) and a portion of the metal layer 72 corresponding tothe source 50 and the drain 52 (hereinafter “second portion”) may bepreferably formed using a lift-off method in which the first portion andthe second portion may be defined by forming the photosensitive patternP1. However, the first and second portions may also be formed using aconventional photographic etching process. For example, the first andsecond portions may be formed by sequentially stacking the metal oxidelayer 70 and the metal layer 72, forming a mask covering regions to beformed as the first and second portions on the metal layer 72, and thensequentially etching the metal layer 72 and the metal oxide layer 70.

After forming the TFT, the TFT may be annealed in a furnace with anitrogen atmosphere between 200° C.˜450° C. for about 1 hour. However,the annealing time may be shorter or longer than 1 hour. Additionally,the annealing may be performed using a rapid thermal annealing (RTA)method or using a laser method.

FIG. 16 is a graph showing source-drain current (I_(ds)) based on thethickness of the metal oxide layer 70 in the TFT according to at leastone example embodiment. The TFT used in FIG. 16 includes the metal layer72 formed of a platinum layer or a titanium layer, and the metal oxidelayer 70 formed of a titanium oxide (TiO₂) layer. A voltage V_(d) thatwas applied to the drain 52 of the TFT was maintained constant at 10 V.

In FIG. 16, a first point A1 is the result of the TFT including themetal layer 72, which corresponds to the source 50 and the drain 52,formed of a platinum layer, and the metal oxide layer 70 formed of atitanium oxide layer having a thickness of 100 Å. Second through fourthpoints A2 through A4 show the source-drain currents in the TFT in whichthe metal layer 72 is a titanium layer.

Referring to the first point A1, when the metal layer 72 is a platinumlayer and the thickness of the metal oxide layer 70 that is formed of atitanium oxide layer is 100 Å, the source-drain current I_(s) is 0 Amps.However, referring to the second through fourth points A2 through A4, ifthe metal layer 72 is a titanium layer and the metal oxide layer 70 is atitanium oxide layer, the source-drain current I_(ds) may besufficiently high. As the thickness of the metal oxide layer 70 islessened, the source-drain current I_(ds) may increase; as the thicknessof the metal oxide layer 70 is increased, the source-drain currentI_(ds) may decrease.

FIGS. 17 through 19 are cross-sectional views of a method ofmanufacturing a TFT according to at least one example embodiment.

In the method of manufacturing the TFT according to at least one exampleembodiment, after forming the channel layer 48, the metal layer 72 maybe formed to be in contact with the channel layer 48, and the metaloxide layer 70 may be formed between the channel layer 48 and the metallayer by annealing the resultant structure. Reference numerals common tothe previous embodiment may denote the same elements described withreference to the previous embodiment.

In detail, processes before forming the channel layer 48 and thephotosensitive pattern P1 for a lift-off process (see FIG. 14) may bethe same as in the method described with reference to the previousembodiment.

After forming the photosensitive pattern P1, the metal layer 72, whichmay have a predetermined or desired thickness, may be formed on anexposed region of the channel layer 48 and the gate insulating layer 46as illustrated in FIG. 17. The metal layer may also be formed on thephotosensitive pattern P1. Then, the photosensitive pattern P1 may belifted off, and accordingly, the metal layer 72 that is formed on thephotosensitive pattern P1 may also be lifted off. After lifting off thephotosensitive pattern P1, as illustrated in FIG. 18, positionscorresponding to the source 50 and the drain 52 of FIG. 2 may be theonly positions where the metal layer 72 remains.

Then, the resultant structure of the TFT illustrated in FIG. 18 may beannealed according to predetermined or desired conditions. Thus, asillustrated in FIG. 19, a metal oxide layer 80 may be formed between themetal layer 72 and the channel layer 48, and the metal oxide layer 80may correspond to the first and second metal oxide layers 54 and 56 ofFIG. 2. A metal included in the metal oxide layer 80 may originate fromthe metal in the metal layer 72. Oxygen included in the metal oxidelayer 80 may be supplied from at least one of the channel layer 48 andoxygen contained in the atmospheric gas during annealing. If the channellayer 48 contains sufficient oxygen to form the metal oxide layer 80,for example, if the channel layer 48 is an oxygen rich GIZO layer, theannealing atmospheric gas may not contain oxygen. The annealing may beperformed at 200° C. to 450° C. Additionally, the annealing may beperformed using not only a furnace, however, also RTA or a laser. Theannealing may be performed for a predetermined or desired period oftime, for example, 1 hour. The atmospheric gas of the annealing maycontain nitrogen (N₂) or oxygen (O₂) according to the annealing method,or only oxygen. By controlling the annealing conditions, the metal oxidelayer 80 may be formed to have the same properties as the metal oxidelayer 70 of the previous embodiment.

When the annealing is completed, the manufacturing process of a TFTaccording to at least one example embodiment may also be finished.

FIGS. 20 and 21 are graphs showing electrical characteristics of a TFTthat was annealed, according to at least one example embodiment.

The TFT whose electrical characteristics are shown in FIGS. 20 and 21may be formed of the metal layer 72 that may be formed by sequentiallystacking a titanium layer and a platinum layer. The metal layer 72 maybe formed to satisfy the geometric conditions of the source 50 and thedrain 52 of FIG. 2, and the annealing may be performed using a furnacein an atmosphere containing nitrogen and oxygen. In FIGS. 20 and 21,first through third graphs G1 through G3 show the characteristicsbetween a gate voltage V_(g) and a source-drain current I_(ds) whenvoltages of 0.1 V, 5 V, and 10 V are applied to the drain 52.

FIG. 20 is a graph showing the results without annealing, and FIG. 21 isa graph showing the results when annealing is performed at 350° C.

Referring to FIG. 20, as the gate voltage V_(g) is increased greaterthan 10 V, a source-drain current is measured, however, the amount ofsource-drain current I_(ds) may be significantly low, and may beregarded as no measured source-drain current I_(ds).

On the other hand, referring to FIG. 21, as the gate voltage isincreased greater than 0 V, a significant amount of source-drain currentI_(ds) may be measured.

As can be seen from the results of FIGS. 20 and 21, when no annealing isperformed in the method of manufacturing a TFT according to exampleembodiment above, a metal oxide layer 80, as illustrated in FIG. 19, maynot form between the metal layer 72 and the channel layer 48. However,when annealing is performed at the above-described temperature, themetal oxide layer 80 may be formed between the metal layer 72 and thechannel layer 48.

FIG. 22 is an image showing the resultant structure in which a siliconoxide layer 90, a channel layer 94, and a metal layer 96 aresequentially stacked and for which an annealing is not performed, andFIG. 23 is an image showing the structure in FIG. 22 where an annealingis performed at 350° C. The silicon oxide layer 90 is a SiO2 layer whichmay correspond to the gate insulating layer 46 of the TFT according tothe at least one example embodiment; the channel layer 94 is a G-I—Z—Olayer which may correspond to the channel layer 48; and the metal layer96 is a Ti/Pt layer which may correspond to the metal layer 72.Reference numeral 99 will be described afterwards.

FIGS. 24 and 25 show the distribution of the material components along aline 1-1′ of FIGS. 22 and 23.

Referring to FIG. 24, after the silicon oxide layer 90, the channellayer 94, and the metal layer 96 are sequentially stacked and theresultant structure is not annealed, about 100 counts of titanium weremeasured (▴) and 60 counts of oxygen are measured (□) in a positioncorresponding to the interface between the channel layer 94 and themetal layer 96.

Referring to FIG. 25, after the silicon oxide layer 90, the channellayer 94, and the metal layer 96 are sequentially stacked and theresultant structure is annealed at 350° C., about 150 counts or more oftitanium were measured and 100 counts or more of oxygen are measured ina position corresponding to the interface between the channel layer 94and the metal layer 96.

As can be seen from the results of FIGS. 24 and 25, in the method ofmanufacturing the TFT described with reference to FIGS. 17 through 19,when the resultant structure of FIG. 18 is annealed at 200˜450° C., newlayer 99 corresponding to the metal oxide layer 80 may be formed betweenthe metal layer 72 and the channel layer 48.

The above-described TFT is a bottom gate type TFT, however, asillustrated in FIG. 26, the example embodiments may also be applied to atop gate type TFT in which the gate 44 may be disposed above the channellayer 48. Additionally, the gate may be buried in the channel layer.

While example embodiments have been particularly shown and described,the example embodiments should be considered in descriptive sense onlyand not for purposes of limitation. For example, it will be understoodby one skilled in the art that annealing may be performed before liftingoff the photosensitive pattern P1. Additionally, various changes in formand details of each element of the TFT may be made or simply a newelement may be inserted between elements. Therefore, the scope of theexample embodiments is defined not by the detailed description of theexample embodiments but by the appended claims.

As described above, the TFT according to example embodiments may includea metal oxide layer between a source and a drain which may be formed ofmetal, and a channel layer which may be formed of an oxidesemiconductor. Accordingly, the TFT may operate in an enhanced mode, andthereby, may reduce its leakage current and increase its carriermobility. As the source and the drain of the TFT may be formed ofgeneral metal, the manufacturing costs may be reduced as compared to theconventional TFT which may use indium for forming a source and a drain.In addition, in the TFT according to at least one example embodiment,contacts to the TFT or wirings connected to the TFT may be formed of thesame material as the source and the drain, and thereby, may decrease theresistance caused by hetero-junction. In addition, the threshold voltageand the source-drain current I_(ds) according to the gate voltage V_(g)may be controlled by controlling the formation conditions of the metaloxide layer, for example, by controlling the thickness of the metaloxide layer.

Example embodiments having thus been described, it will be obvious thatthe same may be varied in many ways. Such variations are not to beregarded as a departure from the intended spirit and scope of exampleembodiments, and all such modifications as would be obvious to oneskilled in the art are intended to be includes within the scope of thefollowing claims.

1. A thin film transistor (TFT) including: a gate; a channel layer; asource and a drain, the source and the drain being formed of metal; anda metal oxide layer, the metal oxide layer being formed between thechannel layer and the source and the drain, wherein the metal oxidelayer has a gradually changing metal content between the channel layerand the source and the drain.
 2. The TFT of claim 1, wherein the metalcontent in the metal oxide layer is gradually increased or decreased ina direction toward the channel layer.
 3. The TFT of claim 1, wherein themetal oxide layer includes a transition metal having an oxidationcharacteristic higher than or similar to that of ZnO.
 4. The TFT ofclaim 3, wherein the transition metal is one selected from the groupconsisting of Ti, Mo, Cr or W.
 5. The TFT of claim 1, wherein the sourceand the drain are double-layers formed of metal.
 6. The TFT of claim 1,wherein the channel layer is an oxide semiconductor layer.
 7. The TFT ofclaim 6, wherein the oxide semiconductor layer is ana(In₂O₃).b(Ga₂O₃).c(ZnO) or a(In203).b(ZnO).c(SnO) (where a, b, and care integers satisfying a≧0, b≧0, and c >0, respectively).
 8. The TFT ofclaim 1, wherein the metal contained in the metal oxide layer is thesame as the metal of the source and the drain.
 9. The TFT of claim 1,wherein the gate is formed above or under the channel layer or buried inthe channel layer.
 10. The TFT of claim 1, wherein the source and thedrain are formed of at least one selected from the group consisting ofTi, Mo, Cr, W, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Co, Sb, V, Ru, Pt, Pd,Zn, and Mg.
 11. The TPT of claim 1, wherein the metal oxide layerincludes a metal oxide which has a single metal, and the content of thesingle metal in the metal oxide gradually increases or decreases betweenthe channel layer and the source and the drain.
 12. The TFT of claim 11,wherein the metal oxide layer is made of a different material from thechannel layer.